1. Field of the Invention
The present invention relates generally to fabrication of semiconductor devices and, more specifically, to the packaging of semiconductor dice.
2. State of the Art
In the field of semiconductor device manufacture, testing and packaging of various types of semiconductor dice are conducted in a similar manner. Thus, conventional dynamic random access memory dice (DRAMs), static random access memory dice (SRAMs), programmable memory dice (PROMs, EPROMs, EEPROMs, flash memories), logic dice, and microprocessor dice are fabricated, tested and packaged in a generally similar manner.
Following fabrication of a plurality of dice on a wafer or other bulk substrate of semiconductor material, a cursory test for functionality is conducted on each die, such as by probe testing. The dice are then singulated, and those passing the functionality test are picked from the wafer, typically for packaging, such as by transfer molding, and subsequent incorporation into a higher-level assembly. Typically, each die is formed with one or more rows of bond pads on the active surface. The bond pad row or rows may be formed along a central axis of the die or along one or more peripheral portions thereof. Transfer molded packages may comprise bond wires which electrically couple bond pads on the die to leads of a lead frame, the outer ends of the leads extending beyond the protective encapsulant, which is typically a silicon-filled, thermoplastic polymer. The lead frame leads are used to achieve mechanical and electric connection of the die to a carrier substrate such as a printed circuit board (PCB), for example.
Following packaging, the packaged die may be characterized for compliance with selected electrical parameters under various environmental conditions. Those which fail the testing are scrapped or, in some instances, may be reworked for compliance using redundant circuitry incorporated into the die.
The foregoing traditional approach to packaging has a number of shortcomings. For example, the resulting package may be much larger than the enclosed die, requiring an undue amount of space or “real estate” on a carrier substrate. In addition, the insulative value of the large mass of encapsulant material of the package inhibits heat transfer from the die, which may cause die malfunction or failure over time. The packaging process is very materials-intensive and requires a substantial number of steps, including adherence of the die to a lead frame of a lead frame strip, wire bonding, placement in a transfer mold cavity and removal therefrom, followed by a trim and form operation to sever the package leads from the lead frame and deform the outer lead ends for connection to higher-level packaging. Furthermore, this type of packaging is somewhat limiting (absent somewhat exotic lead frame design approaches) in terms of the number of available I/O connections, presenting a problem as the number of required connections per die increases.
A board-on-chip (BOC) semiconductor package has also been developed, in which an interposer substrate such as a relatively small, slightly larger than die-size interposer substrate is formed with a centrally placed, elongate through-slot sized and configured for alignment with a row or rows of bond pads on the die. The through-slot is also known as an “interconnect slot” or “wire bond slot.” The die is adhesively joined by its active surface to one side of the interposer substrate such that the bond pads are accessible through the interconnect slot. The bond pads are connected to conductive traces on the opposite side of the interposer substrate, by bond wires, for example, which pass through the interconnect slot. The interconnect slot is then filled with a filled polymer encapsulant to encase and seal the bond wires and surrounding, exposed portion of the die's active surface. Conventionally, a transfer molding process is used to form this wire bond mold cap while simultaneously encapsulating the back side and sides of the die on the opposite side of the interposer substrate. A ball grid array (BGA) or other type of array of discrete conductive elements electrically connected to the conductive traces and projecting from the side of the interposer substrate with the wire bond cap may be used to mechanically and electrically connect the package to a carrier substrate or other higher-level packaging. Various examples of this type of package construction are shown in U.S. Pat. Nos. 5,723,907 and 5,739,585 to Akram and U.S. Pat. No. 5,818,698 to Corisis, all of which patents are assigned to the assignee of the present application and the disclosure of each of which is incorporated by reference herein. The resulting package has a much reduced size, which may be termed “chip scale” or “near chip scale,” and is generally capable of establishing robust, high-quality mechanical and electrical connections using conventional bonding techniques.
Various aspects of the general concept of the above-described type of package are also shown in U.S. Pat. No. 5,313,096 to Eidc, U.S. Pat. No. 5,384,689 to Shen, U.S. Pat. No. 5,661,336 to Phelps, Jr. et al., and U.S. Pat. No. 6,190,943 B1 to Lee et al.
Despite the obvious advantages for this BOC-type of semiconductor package, a problem has been repeatedly noted relative to the integrity of the wire bond mold cap. Stress cracking of the wire bond mold cap has been found to occur at an unacceptably high frequency in certain package configurations, which stress cracking has been found to be attributable to tensile stresses induced in the interconnect or wire bond slot region during temperature cycling, thermal shock, curing in the mold during the encapsulation process, etc., as the package interposer substrate is cycled between compressive and tensile stress states. This cycling is due in large part to the disparity in encapsulant volume on opposing sides of the interposer substrate and the associated stress cracking to reduced rigidity against bending of the interposer substrate due to the presence of the interconnect or wire bond slot extending along a majority of the centerline or longitudinal axis of the interposer substrate.
The aforementioned stress cracking in conventional BOG-type packages has been found to be largely concentrated at the interface between the interconnect slot edge and the mold cap itself. It has been recognized that the magnitude and frequency of occurrence of this problem is greater where the length of the elongated, central interconnect slot is a major portion of the corresponding substrate length. In BOC-type packages having an interposer substrate with an interconnect slot, the interconnect slot length is typically about 70 to 80% of the corresponding substrate length. It has been estimated that an unacceptably high failure rate generally occurs where the slot length is about 67% or more of the substrate length (for a bismaleimide triazine (BT) resin substrate). Thus, the problem may be very pervasive, as such relative slot lengths are quite common and necessary to accommodate the large number of bond pads required for operation of state of the art dice. Where the interposer substrate comprises another material, such as a ceramic for example, the critical ratio of slot length to substrate length may be somewhat different.
The present invention is directed to effectively resolving the foregoing problem in an economic manner using conventional components and packaging techniques.